An improvement on NMOS and PMOS inverters (they draw current in their ON state and have relatively high output impedance in their OFF state) is the CMOS (Complementary MOSFET) inverter shown above.
Input grounded (input LOW) switches OFF the bottom NMOS M2 and turns ON the top PMOS M1, pulling the output HIGH. Input HIGH switches OFF the top PMOS M1 and switches ON the bottom NMOS M2, pulling output LOW. The CMOS is an inverter with low output impedance in both states, no quiescent current, swings to the full supply range and is the basic structure of all digital CMOS logic (from The Art Of Electronics, Paul Horowitz, Winfield Hill, ISBN: 0-521-37095-7).
Let's do a SPICE simulation of the circuit, here is the netlist for the circuit above (you have to manually enter the body pin for the symbols I have used in the schematic, there are other symbols with a separate body pin but I feel they are too simplified when beginning with MOSFETs):
Transient Analysis (Vin 0):
tran 0.01m 10m
Transient Analysis (Vin 5):