NAND

gschem Screenshot

A logic NAND (NOT AND) gate is shown above. The output goes LOW only if inputs A AND B are both HIGH. If A and B are both HIGH, series NMOS switches M1 and M2 are both ON, pulling output to ground (LOW), with PMOS switches M3 and M4 OFF and thus no current flows. If A or B (or both) is LOW, the corresponding PMOS transistor is ON, pulling the output HIGH. With the series NMOS M1 M2 OFF, no current flows. To get an AND gate, you just invert the output (maybe with a CMOS inverter!) (from The Art Of Electronics, Paul Horowitz, Winfield Hill, ISBN: 0-521-37095-7).

Netlist of circuit:

Pluma Screenshot 1

Transient Analysis (Vin1 and Vin2 5V):
tran 0.01m 10m

Ngspice Screenshot 1

Transient Analysis (Vin1 5V and Vin2 0V):

Ngspice Screenshot 2

Transient Analysis (Vin1 0V and Vin2 5V):

Ngspice Screenshot 3

Transient Analysis (Vin1 0V and Vin2 0V):

Ngspice Screenshot 4